The present invention relates generally to the field of low voltage, high current DC power supplies. More particularly, the present invention relates to utilization of asymmetrical, normally off Junction Field Effect Transistors (JFET) to construct two terminal rectifier circuits useful in low voltage and high current density DC power supply circuits.
The increasing trend toward lower supply voltages for active semiconductor devices and Integrated Circuits (IC""s) has accelerated the search for more efficient low voltage power sources. Conventional power supplies utilizing silicon diode rectifiers are unacceptable in low voltage applications due to the excessive voltage drop across the forward biased diode terminals. Power loss in the diodes becomes excessive when they are used as rectifiers in a DC power supply designed for a terminal voltage as low as 3.0 volts.
Semiconductor diodes are combined with active devices to form circuits capable of producing low value DC supply voltages, but such circuits are generally not capable of handling the large currents frequently required. They usually exhibit a fairly large internal resistance and as such are very inefficient power sources. Furthermore, the number and complexity of steps required in the processing of this type of circuit as an IC also increases with the number of devices included.
Active semiconductor devices are used as switches in circuit arrangements producing DC power supply voltages, as for example in switched mode power supplies. Junction Field Effect Transistors (JFET) are frequently used as switches because they are easily switched between an ON or conducting state and an OFF or non-conducting state. Most importantly, the current carriers in a JFET are all majority carriers which results in short switching times. However, when operated at lower voltages, JFETs exhibit an internal resistance in the ON state that make them unsatisfactory and inefficient in applications requiring large currents.
In U.S. Pat. No. 4,523,111 entitled xe2x80x9cNormally-Off Gate-Controlled Electric Circuit with Low On-Resistancexe2x80x9d, Baliga disclosed a JFET serially connected to an Insulated Gate Field Effect Transistor (IGFET). The ON resistance of this circuit is the sum of the JFET resistance and the IGFET resistance. As a result, the ON resistance is too large and therefore unsatisfactory for low voltage operations requiring large currents.
In a similar invention disclosed in U.S. Pat. No. 4,645,957 entitled xe2x80x9cNormally Off Semiconductor Device with Low On-Resistance and Circuit Analoguexe2x80x9d by Baliga, a JFET is serially connected to a Bipolar Junction Transistor (BJT). The ON resistance is the sum of the JFET and the BJT which is again too large for low voltage applications requiring large currents.
In an invention disclosed in U.S. patent application Serial No. 60/167,959, xe2x80x9cSTARTER DEVICE FOR NORMALLY xe2x80x9cOFFxe2x80x9d JFETSxe2x80x9d, Ho-Yuan Yu, filed Nov. 29, 1999, a normally OFF JFET is combined in parallel with one or more active devices defined as starter devices. In a first case, a BJT acting as the starter device is connected in parallel with the normally OFF JFET. In a second case, a Metal Oxide Silicon Field Effect Transistor (MOSFET) acting as the starter device is connected in parallel with the normally OFF JFET. In a third case, three normally OFF JFETs are connected serially as a starter device, and are then connected in parallel with the normally OFF JFET. Each of the resulting structures provide high current carrying capacity at low voltage levels, but still exhibit a larger than desired internal resistance in the ON or conducting state. Furthermore, the required starter devices all necessitate an increase in the number of steps and in the complexity of the IC processing recipe.
Accordingly, what is needed is a semiconductor circuit that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages. What is further needed is a two terminal semiconductor circuit that can be used to replace the semiconductor diodes used in conventional DC power supply circuits. What is also needed is a two terminal semiconductor circuit that has a very low internal resistance such that the power dissipated in the circuit itself is only a fraction of that delivered to a connected load. What is needed yet is a two terminal semiconductor circuit that exhibits short switching times between an on or conducting state and an off or non-conducting state. The present invention provides these advantages and others not specifically mentioned above but described in the sections to follow.
A semiconductor circuit that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages is disclosed. In the present invention, an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET) is utilized as a two terminal device by connecting together the gate and source leads. With an external voltage applied between source and drain with a polarity that will forward bias the p-n junctions between gate and drain, low resistance, current conducting channels are formed between source and drain. This is the on or current conducting state. The forward voltage drop of this configuration is approximately the threshold voltage of the normally off JFET. With an external voltage applied between source and drain with a polarity that will reverse bias the p-n junctions between gate and drain, the built-in p-n junction depletion regions will isolate the source and drain leads to prevent the conduction of electric current between source and drain. This is the off or non conducting state. Thus, this two terminal device has a forward or current conducting state and a reverse or non current conducting state similar to a conventional semiconductor diode.
In a second configuration, an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET) is connected with a transformer such that the source and the drain serve as the two leads of a two terminal circuit. The primary of the transformer is connected between the drain and source leads, while the secondary is connected between the gate and source leads. The transformer is connected such that a voltage induced at the secondary is greater than and 180 degrees out of phase with the primary voltage. With an external voltage applied between source and drain with a polarity that will forward bias the p-n junctions between gate and source, low resistance, current conducting channels are formed between source and drain. This is the on or current conducting state. With an external voltage applied between source and drain with a polarity that will reverse bias the p-n junctions between gate and source, the built-in p-n junction depletion regions will isolate the source and drain leads to prevent the conduction of electric current between source and drain. This is the off or non conducting state. Thus, this two terminal circuit has a forward or current conducting state and a reverse or non current conducting state similar to a conventional semiconductor diode. The voltage drop between source and drain when in the on or current conducting state is considerably smaller than that obtained by simply connecting the source directly to the gate. This reduced source to drain voltage is due to the larger forward bias voltage applied between gate and source.
In a third configuration, an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET) is connected with a voltage step up circuit such that the source and the drain serve as the two leads of a two terminal circuit. The voltage step up circuit senses the potential difference between source and drain and produces a larger potential difference between a third terminal and the terminal connected to the source. This third terminal is connected to the gate and has a polarity with respect to the source that is 180 degrees out of phase with the potential difference at the drain with respect to the source. With an external voltage applied between source and drain with a polarity that will forward bias the p-n junctions between gate and drain, low resistance, current conducting channels are formed between source and drain. This is the on or current conducting state. With an external voltage applied between source and drain with a polarity that will reverse bias the p-n junctions between gate and drain, the built-in p-n junction depletion regions will isolate the source and drain leads to prevent the conduction of electric current between source and drain. This is the off or non conducting state. Thus, this two terminal circuit has a forward or current conducting state and a reverse or non current conducting state similar to a conventional semiconductor diode. The voltage drop between source and drain when in the on or current conducting state is considerably smaller than that obtained by simply connecting the source directly to the gate.